Analysis of non-idealities in parallel-summation logarithmic amplifiers

Literals

• vivo:identifier
  • 2017-4066
• dcterms:title
  • Analysis of non-idealities in parallel-summation logarithmic amplifiers
• ou:bibtex
  • @article{Ausín2017,title = {Analysis of non-idealities in parallel-summation logarithmic amplifiers},journal = {2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016},year = {2017},pages = {556-559},author = {Ausin, J.L. and Ramos, J. and Duque-Carillo, J.F. and Torelli, G.}}
• ou:eid
  • 2-s2.0-85015333928
• ou:tipoPublicacion
  • Conference Paper
• dcterms:contributor
  • Ausin, J.L.; Ramos, J.; Duque-Carillo, J.F.; Torelli, G.
• dcterms:publisher
  • 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
• bibo:page_range
  • 556-559
• bibo:doi
  • 10.1109/icecs.2016.7841262
• dcterms:creator
  • Ausin J.L.
• fabio:hasPublicationYear
  • 2017
• bibo:isbn
  • 9781509061136
• vcard:url
  • https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85015333928&origin=inward
• ou:urlOrcid
  • http://www.scopus.com/inward/record.url?eid=2-s2.0-85015333928&partnerID=MN8TOARS
• ou:urlScopus
  • https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85015333928&origin=inward

Typed Literals

• dcterms:created
  • 2016-01-01T00:00:00 (xsd:dateTime)
• ou:vecesCitado
  • 3 (xsd:integer)

Inverse Relations

• Has related: ou:tienePublicacion
  • JOSÉ LUIS AUSÍN SÁNCHEZ
  • JUAN FRANCISCO DUQUE CARRILLO