PUBLICACIÓN
High-speed reconfigurable parallel system to design good error correcting codes in communications
Gomez-Pulido J.A., Vega-Rodriguez M.A., Sanchez-Perez J.M.
2012 Journal of Signal Processing Systems
Control and Systems Engineering (Q3), Hardware and Architecture (Q3), Information Systems (Q3), Modeling and Simulation (Q3), Signal Processing (Q3), Theoretical Computer Science (Q4)
JCR: 0.551
SJR: 0.269
CITAS
3
DOI
10.1007/s11265-011-0626-6
EID
2-s2.0-84856736047
ISSN
1939-8018
EISSN
1939-8115
BIBTEX
@article { gomezpulido2012,title = {High-speed reconfigurable parallel system to design good error correcting codes in communications},journal = {Journal of Signal Processing Systems},year = {2012},volume = {66},number = {2},pages = {147-152},author = {Gómez-Pulido, J.A. and Vega-Rodríguez, M.A. and Sánchez-Pérez, J.M.}}
AUTORES DE LA UEX